As a micro memory which has already put into practical use, there is a DRAM (Dynamic RAM) in which one cell has a 1T (Transistor)/1C (Capacitor) structure. At present, using a 40 nm to 30 nm generation process, a product having a cell size of 6F2 (F: Feature Size, half pitch of a bit line and a word line) is being mass-produced (for example, see Y. K. Park et al., “Fully Integrated 56 nm DRAM Technology for 1 Gb DRAM”, “2007 Symposium on VLSI Technology Digest of Technical Papers”, p. 190-191, and Changhyun Cho et al., “A 6F2 DRAM Technology in 60 nm era for Gigabit Densities”, “2005 Symposium on VLSI Technology Digest of Technical Papers”, p. 36-37).